System on Chip (SoC) platforms have become the de facto enabling technology for mobile multimedia personal communication and entertainment embedded systems. Among various architecture choices, application-specific instruction-set processors (ASIP) that incorporate sub-word parallelism provide a low-cost high-performance solution particularly suitable for manipulating short word-length multimedia data streams.
Hardware Software Co-Design of a Multimedia SOC Platform is one of the first of its kinds to provide a comprehensive overview of the design and implementation of the hardware and software of an SoC platform for multimedia applications. Topics covered in this book range from system level design methodology, multimedia algorithm implementation, a sub-word parallel, single-instruction-multiple data (SIMD) processor design, and its virtual platform implementation, to the development of an SIMD parallel compiler as well as a real-time operating system (RTOS).
Hardware Software Co-Design of a Multimedia SOC Platform is written for practitioner engineers and technical managers who want to gain first hand knowledge about the hardware-software design process of an SoC platform. It offers both tutorial-like details to help readers become familiar with a diverse range of subjects, and in-depth analysis for advanced readers to pursue further.
