As Moore's law continues to unfold, two important trends have recently emerged. First, the growth of chip capacity is translated into a corresponding increase of number of cores. Second, the parallalization of the computation and 3D integration technologies lead to distributed memory architectures.
This book provides a current snapshot of industrial and academic research, conducted as part of the European FP7 MOSART project, addressing urgent challenges in many-core architectures and application mapping. It addresses the architectural design of many core chips, memory and data management, power management, design and programming methodologies. It also describes how new techniques have been applied in various industrial case studies.
- Describes trends towards distributed memory architectures and distributed power management;
- Integrates Network on Chip with distributed, shared memory architectures;
- Demonstrates novel design methodologies and frameworks for multi-core design space exploration;
- Shows how midlleware services (dynamic data management) can be integrated into and support by the platform.
From the reviews:
"This book presents to the general public the most important results from the Mapping Optimization for Scalable Multi-core Architecture (MOSART) research project, which was carried out between 2008 and 2010 (three years). It is quite brief and organized into three parts. ? this book is well organized and balanced. Each chapter is self-explanatory and can be studied separately. The book as a whole is a good demonstration of engineering. It deserves to be recommended to professionals and research students in the area." (D. Grigoras, ACM Computing Reviews, June, 2012)
